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About n-hop

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n-hop technologies Limited is a technology startup. Two of our founders invented the BATched Sparse Code (BATS), a disruptive coding scheme in Data Networking. The technology has obtained 10 patents with another one pending. The company started to commercialize the technology in 2019 by implementing the coding algorithm into a software that operates in an Industrial processor. Our plan is to populate the technology into a wide variety of data communication devices. These include all types of wired/ wireless equipment and IoT devices. We invite highly motivated and talented individuals to join us and progress together in this exciting invention.

"To be the most successful leader in the development and use of Network Coding technologies. We strive to achieve worldwide recognition, adoption and use of the BATS coding scheme."

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Raymond Yeung, Shenghao Yang, Founders of n-hop  

We are looking for:

We are looking for:


Software Engineer

To develop a new generation of network communication systems.

  • Bachelor/Master/Ph.D. degree in Computer/Electronics/Information Engineering, or other related majors and at least three years of post-qualification experience

  • Experience in the product development life cycle and product release management

  • Strong hands-on and experience in C, C++ programming in Linux operating systems especially on networking software development


Project Engineer

In charge of one or multiple projects at a time and can co-lead or be an assistant alongside a project manager, giving advice and supervision to the engineering and management aspects of the project.

  • BSc. in Computer Science or Electrical Engineering with 3 years of relevant experience as a Project Engineer

  • Training and or qualification in project management

  • Confident decision-making ability


FPGA Design Engineer

To implement real-time DSP algorithms using FPGA.

  • BS/Master with 2+ years of relevant experience as an FPGA engineer in an R&D environment

  • Experience working with Xilinx/Intel parts and Vivado design tools including synthesis, implementation and timing closer, and working knowledge of the VHDL and Verilog language

  • Experience in bench testing and debugging FPGA designs

Send your CV to: